The present invention relates to integrated circuits including power and logic transistors on the same chip. It more particularly relates to an integrated circuit including a power transistor, a lateral MOS logic transistor and a Schottky diode and to a method of forming same.
FIG. 1 is a schematic section view of an integrated circuit described in European Application 87/00325.4 in the name of Thomson CSF. For the sake of simplicity only certain elements of this structure are illustrated (particularly certain thin and thick oxide layers are not shown). In the right-hand portion of FIG. 1 is an illustration of a cell of a power VDMOS (vertical diffused MOS) transistor 1 of the enhancement-mode type and in the left-hand portion of the figure are represented logic components such as a depletion-mode N-channel lateral MOS transistor 2 and an enhancement-mode N-channel lateral MOS transistor 3.
This structure is made on a substrate comprising an N-type layer 10 epitaxially grown on an N.sup.+ -type silicon wafer 11.
In a first doping step are formed P-type regions 12, especially corresponding to wells wherein the logic portion of the chip is formed.
In a second doping step, P.sup.+ regions with a high doping level are formed, this doping level being high enough to obtain ohmic contacts with metallizations The P.sup.+ regions enable an ohmic contact with well 12 and regions 18 of the power VDMOS transistor to be formed to obtain contact with a so-called "bulk" region in an upper region where the channel is formed
In a third doping step are formed N-type regions 13 especially corresponding to channel regions of the depletion-mode lateral MOS transistors.
Then, one conventionally forms (for example through oxidation, deposition of polycrystalline silicon, etching and reoxidation) gates 21 of the power transistor, gates 22 of the enhancement-mode lateral MOS transistors and gates 23 of the depletion-mode lateral MOS transistors. Gates 21 and 22 are simultaneously formed during this step.
A fourth P-type doping step in the region of the VDMOS transistor forms the channel regions 30 of those transistors with the gate regions acting as a mask.
Then, in a fifth doping step, one forms, by using the above-mentioned gates as a mask, N.sup.+ regions especially corresponding to the sources 32 of the power transistor and to the sources and drains 33-36 of the depletion-mode and enhancement-mode lateral MOS transistors.
Lastly, after oxidation and opening of appropriate windows, one forms a metallization layer wherein one etches the source metallization 41 of the power transistor and the source and drain metallizations 42-45 of the lateral transistors as well as other metallizations such as contact metallizations 46 of the wells wherein are formed logic components.
The rear surface of the component which corresponds to the drain of the VDMOS transistor 1 is coated with metallization 48.
In operation, such a structure is generally connected so that its rear surface 48 is at the highest positive voltage (+V.sub.HT), all the other metallizations being at lower voltages and the metallization 46 of well 12 being usually grounded.
The above described structure is particularly advantageous due to its simplicity. Indeed, it requires a minimum number of masking and doping steps. As seen previously, only five doping types are used. However, this simplicity enables only a limited number of components to be realized in such a structure.
The user usually desires, while maintaining the low cost and reliability associated thereto, to have additional elementary components, such as for example PN diodes that are biased to operate in the forward direction (conductive with a voltage on the P region higher than the voltage on the N region).
FIG. 2 is an elementary drawing of a prior art embodiment of such a PN diode in a structure of the type shown in FIG. 1. The PN diode is formed between the enhancement-mode P region of well 12 and N.sup.+ region 50 formed in well 12. The upper surface of N.sup.+ region 50 is coated with metallization 51, and P.sup.+ region 52 (formed in well 12) is coated with metallization 53. Thus, a diode able to operate in the forward direction between metallizations 53 and 51 is effectively obtained.
However, in practical implementations, such a structure cannot be used. According to a first drawback, the well would be at a voltage set by the connection to metallization 53 and would no longer be maintained at ground, as is desirable. A second drawback of this prior art arrangement is that when the PN diode is conductive and current flows from metallization 53 towards metallization 51, this current constitutes the base current of parasitic NPN transistor 54. The emitter, base and collector of parasitic transistor 54 respectively correspond to (a) region 50, (b) well 12 and (c) the N/N.sup.+ substrate connected to metallization 48. Parasitic transistor 54 is a high quality transistor, that is, it has a high gain. If this gain is about 20-50, each time current flows between metallizations 53 and 51, a current 20 to 50 times higher would flow between metallizations 48 and 51. This current in the parasitic transistor flows parallel to the current flowing in power component 1. The current in parasitic transistor 54 is liable to have a very high amplitude which would cause the structure to be overheated and possibly destroyed.
Thus, it is not possible to realize in a simple way, with the above mentioned technology, diodes able to operate in the forward direction. To solve this problem the prior art has resorted, either to (1) more complex technologies by adding additional wells but without completely solving the problems associated with parasitic transistors, or (2) so-called active diode structures wherein a polarity detection causes an MOS transistor to become conductive. This second method may prove satisfactory but requires relatively complex circuits which necessitate an important silicon surface.
Thus, an object of the invention is to solve the encountered problem by using only five doping steps and a single metallization step including VDMOS-type vertical power MOS transistors and lateral logic transistors, and to the resulting structure to form a diode in an integrated circuit.